1. Field of the Invention
The present invention relates to a semiconductor memory device, and in particular, to a well structure in a NAND-type flash EEPROM (Electrically Erasable and Programmable Read Only Memory) device having a plurality of memory cell transistors for storing data and select transistors for selecting the memory cell transistors, and a method for fabricating the same.
2. Description of the Related Art
Semiconductor memory devices are largely divided into RAMs (Random Access Memories), such as DRAMs (Dynamic RAMs) and SRAMs (Static RAMs), and ROMs (Read Only Memories). RAMs, also referred to as volatile memories because the stored data is destroyed with the passage of time, allow rapid data storage and data retrieval. ROMS, also referred to as nonvolatile memories because they retain data once it is entered, typically have slower data storage and data retrieval times.
Among ROMs, demands are increasing for EEPROMs, in which data is electrically programmed and erased. A flash EEPROM, which is electrically erasable at high speed without being removed from a circuit board, offers the advantages of a simple memory cell structure, cheap cost, and no need for a refresh signal to retain data.
Flash EEPROM cells are largely divided into two types: a NOR type EEPROM and a NAND type EEPROM. A NOR type EEPROM requires one contact in every two cells, which is not favourable for high scale integration, but has a large cell current, and is therefore capable of high-speed operation. A NAND type EEPROM is typically not capable of such high-speed operation due to a small cell current, but it shares one contact in a plurality of cells and thus is useful in realizing high scale integration. Therefore, the NAND flash EEPROM has attracted interest as a next generation memory device for use in digital still cameras and similar devices.
FIG. 1 is a sectional view of a cell array structure in a conventional NAND flash EEPROM, and FIG. 2 is an equivalent circuit diagram of the cell array (see, Symposium on VLSI Circuits, 1990, pp. 105-106).
Referring to FIGS. 1 and 2, a single string is composed of a string select transistor SST for selecting a unit string, a ground select transistor GST for selecting the ground, and a plurality of memory cell transistors connected in series between the string select transistor SST and the ground select transistor GST. A bit line is connected to the drain of the string select transistor SST and a common source line CSL is connected to the source of the ground select transistor GST. One block is comprised of a plurality of strings connected in parallel to bit lines, and such blocks are symmetrically arranged with respect to a bit line contact.
A memory cell transistor includes a stack comprised of a floating gate 18, formed on a semiconductor substrate 10 with interposition of a tunnel oxide film 16, and a control gate 22, formed on the floating gate 18 with interposition of an interlayer dielectric layer 20. The floating gate 18 extends across an active region and across edge portions of the field regions at both sides of the active region, thus being isolated from a floating gate 18 in an adjacent cell. The control gate 22 is connected to that of an adjacent cell, forming a word line W/L.
A string select transistor requires no floating gate for storing data, and thus its floating gate 18 and control gate 22 are connected by a metal wire through a butting contact on a field region in a cell array. Therefore, the string select transistors act as MOS transistors electrically having a single-layer gate structure.
A general NAND flash EEPROM cell array as constituted above is produced by forming an n-well 12 on a p-substrate 10 and then forming a p-well 14 (pocket p-well 14) inside the n-well 12. A description of the cell operation will hereinbelow be described.
For programming a selected cell, 0 V is applied to a bit line connected to the selected cell and a program voltage V.sub.pgm is applied to a word line connected to the selected cell, so that electrons are injected into the floating gate 18 due to the voltage difference between the channel and the control gate 22 of the memory cell transistor. Here, a pass voltage V.sub.pass is applied to unselected cells among a plurality of memory cells between the bit line and a ground node, to transfer data (i.e., 0 V) applied to the selected bit line to the selected cell.
For example, when V.sub.pgm =20 V is applied to the word line of a selected cell A, V.sub.pass =10 V is applied to the word lines for the unselected cells in the string and to the string select transistor SST, 0 V is applied to a selected bit line and a ground select transistor GST, and a program inhibit voltage V.sub.pi =10 V is applied to an unselected bit line, then electrons are injected into the floating gate 18 through the tunnel oxide film 16 from the p-well 14 due to the V.sub.pgm of the selected cell A.
For erasing a cell, that is, removing electrons stored in the floating gate 18 , an erase voltage V.sub.erase =20 V is applied to the p-well 14 , and 0 V is applied to a word line connected to the selected cell. Electrons are removed from the floating gate and holes are injected thereinto by an electrical field generated by V.sub.erase which has a reverse polarity to that applied during the programming operation. To prevent V.sub.erase applied to the p-well 14 during the erasing operation from affecting a peripheral circuit, the memory cell array is formed in the pocket p-well 14 in the n-well 12 .
Data "0" or "1" is read from a selected cell according to the presence or absence of a current path through a selected cell, relying on the principle that the threshold voltage V.sub.th of the cell is changed to +1 V when electrons are stored in the cell, while the threshold voltage V.sub.th is changed to -3 V when holes are stored in the cell.
To inhibit an unselected cell B connected to the unselected bit line and the selected word line from being programmed in the above NAND flash EEPROM cell array, a voltage V.sub.pi =10 V applied to the unselected bit line is directly induced to the channel of the unselected cell B by V.sub.pass applied to the unselected word line, thereby reducing the V.sub.pgm -induced electrical field and thus preventing F-N (Fowler-Nordheim) tunneling.
Because V.sub.pi is higher than the supply voltage V.sub.cc (3.3 V or 5 V), V.sub.pi should be produced by charge pumping using a capacitor. Charge pumping refers to generation of a required voltage by accumulating potential in a capacitor. As the required current capacity of the generated voltage increases, the capacitor requires a larger area. This increases the chip area required for forming the capacitor and increases the programming time, due to the time needed to charge the bit line voltage capacitor with V.sub.pi. Both of these effects are undesirable.
Accordingly, to avoid application of a higher voltage than V.sub.cc to the unselected bit line, a method has been suggested in which V.sub.cc is applied to the unselected bit line and the string select transistor SST, V.sub.pgm is applied to the selected word line, V.sub.pass is applied to the unselected word lines, and 0 V is applied to the selected bit line, the well, and the ground select transistor GST, to thereby self-boost V.sub.pi to the channels of unselected strings (see, IEEE Journal of Solid State circuits, 1995, pp. 1149-1156).
According to the self-boosting scheme, the charge pump capacitor area needed to increase the bit line voltage can be reduced and charging time of the bit line voltage also reduced by applying V.sub.cc, set to a maximum voltage, to a bit line and only applying a voltage larger than V.sub.cc to a word line. As a result, chip performance can be enhanced.
A description of a method of self-boosting a channel voltage to inhibit programming of a string cell will be given as follows.
Assuming that a floating gate is set to a neutral state, an average channel voltage (about 7 V) in a cell of an unselected bit line is calculated by ##EQU1## where V.sub.ch.sel is a channel voltage of an unselected cell connected to a selected word line, obtained by ##EQU2##
In addition, the channel voltage V.sub.ch.unsel of an unselected cell connected to an unselected word line is expressed as ##EQU3## where C.sub.ch is a depletion capacitance generated by a depletion region formed under the channel, and C.sub.ins is a total capacitance between the control gate and the channel, defined as: ##EQU4##
V.sub.prechg, being about 1.5 V when V.sub.cc is 3.3 V, is precharged to the channel from the bit line before the programming operation is initiated, and is defined by: EQU V.sub.prechg =V.sub.cc -V.sub.th ' (5)
where V.sub.th ' is the threshold voltage of an string select transistor SST when a back bias is V.sub.cc.
As can be seen from equation (5), as V.sub.th ' increases, that is, as the body effect of the string select transistor SST becomes greater, V.sub.prechg precharged in the cell becomes smaller. Thus, a larger disturbance is imposed on the unselected cell, decreasing reliability. In addition, because the channel width of the string select transistor SST gets smaller in a higher-integration device, a narrow width effect causes the threshold voltage to increase, in turn increasing the body effect.
A method for reducing this narrow width effect is disclosed in U.S. Pat. No. 4,633,289 and No. 5,428,239.
According to U.S. Pat. No. 4,633,289, latch-up is suppressed by forming a retrograde well and thus reducing substrate resistance. Thus, the narrow width effect of a transistor is decreased, reducing the body effect and increasing the effective channel width. As a result, the current driving capability can be substantially increased. Furthermore, C.sub.ch is reduced by reducing the junction capacitance in a cell, so that V.sub.ch.sel and V.sub.ch.unsel are increased, in turn increasing V.sub.ch.avg, and as a result, boosting efficiency is increased. Therefore, stresses caused by V.sub.pgm and V.sub.pass on unselected cells become smaller, enabling a cell of high reliability to be obtained.
According to this technique, the retrograde well is formed by high-energy ion-implantation, causing an impurity concentration peak to be observed at a predetermined depth of the substrate, such that the impurity concentration decreases nearer to the surface of the substrate. The formation of the retrograde well requires no high-temperature, long-time diffusion typically used for a diffusion well, thereby contributing to reduction of process cost, and reducing latch-up and soft error rate, thereby increasing device reliability.
According to U.S. Pat. No. 5,428,239, a retrograde well is formed in a memory cell array region, whereas a diffusion well is formed in a peripheral circuit region, to optimize characteristics of memory cells and peripheral circuit transistors.
A method of forming both a pocket p-well (or pocket n-well) and an n-well (or p-well) surrounding it as retrograde wells is described in IEEE Transactions on Electronic Devices, 1984, Vol. ED-37, No. 7, pp. 910-919. However, in this case, the electrical field is increased due to a high peak concentration, resulting in a decrease in the breakdown voltage between the pocket p-well and a p-substrate. As described above, because an erasing operation for a general NAND-type flash EEPROM cell is performed by applying an erase voltage V.sub.erase =20 V to both the pocket p-well and the n-well, the breakdown voltage between the pocket p-well and the p-substrate should be higher than V.sub.erase.